1. Field of the Invention
The present invention relates to a data transfer method performed in a data processor for processing a packet data.
In a data processor for processing a packet data in a switching system being for switching telephone information or data, the packet data to be transmitted from the data processor has various length, a short length like several bytes and a long length like several kilo bytes as seen in a call control packet and a data transfer packet respectively.
However, a main memory in the data processor cannot store a packet data having such longest length in a single memory because a memory is generally required to store a limited length like 256 bytes in consideration of the utilization efficiency of the memory. Therefore, when the length of a packet data is more than a limited length, the packet data is divided to a plurality of data blocks so that each data block has less than the limited length. Accordingly, the main memory is divided to a plurality of buffer memory regions so that each region stores a data having less than the limited length. As doing so, the packet data can be stored in the main memory with the high utilization efficiency.
2. Description of the Related Art
FIG. 1 is a block diagram of a data processor 100. In FIG. 1, data blocks and commands used in carrying out the data transfer method of the related art are illustrated in a main memory 2. The state of the data block transferred by the related art method is shown in FIG. 2, and a transfer process of the data blocks performed by the related art method with the associated commands is shown in FIG. 3.
In FIG. 1, data processor 100 comprises a central control equipment 1, a main memory 2, a channel control equipment 3 and a plurality of line control equipments 5. The central control equipment 1 is for controlling the division of the packet data to the data blocks and the transfer of the data blocks. Main memory 2 is for storing the data blocks and various commands for the transfer of the data blocks. Channel control equipment 3 is for controlling data transfer performed through a common bus 4 and a plurality of line control equipments 5, one of which is depicted in FIG. 1, are for controlling the receive and transmit of the packet data in data processor 100.
In main memory 2, a plurality of buffer memory regions, four buffer memory regions 23.sub.1, 23.sub.2, 23.sub.3 and 23.sub.4 are shown in FIG. 1 representatively, are provided for storing the data blocks so that each buffer memory region has a previously designated buffer memory length m like 256 bytes.
In FIGS. 1, 2 and 3, when data processor 100 receives a packet data D.sub.1 having data length n.sub.1 larger than m, packet data D.sub.1 is divided to a plurality of partial data SD.sub.11, SD.sub.12, SD.sub.13 and SD.sub.14 so as to have data lengths 1.sub.11, 1.sub.12, 1.sub.13 and 1.sub.14 respectively, and data blocks DB.sub.11, DB.sub.12, DB.sub.13 and DB.sub.14 are formed by adding headers H.sub.11, H.sub.12, H.sub.13 and H.sub.14 to partial data SD.sub.11, SD.sub.12, SD.sub.13 and SD.sub.14 respectively. Headers H.sub.11, H.sub.12, H.sub.13 and H.sub.14 specify information such as an arranged order of partial data in the packet data and a data length of the corresponding partial data respectively. Data blocks DB.sub.11, DB.sub.12, DB.sub.13 and DB.sub.14 are stored in buffer memory regions 23.sub.1, 23.sub.2, 23.sub.3 and 23.sub.4. When a last data block in the train of the data blocks such as DB.sub.14 has a lack of data length to the memory length m, an invalid data N.sub.1 is added for filling the lack.
The central control equipment 1 further provides write commands WRT.sub.1, WRT.sub.2, WRT.sub.3 and WRT.sub.4 and read commands called "read patterns on transmission ports" TRPT.sub.1, TRPT.sub.2, TRPT.sub.3 and TRPT.sub.4, for data blocks DB.sub.11, DB.sub.12, DB.sub.13 and DB.sub.14. These write and read commands are stored in a command language memory region 22 in main memory 2 respectively as shown in FIG. 1. The write command is for designating a transfer condition of the corresponding data block such as a transfer direction, a storing address and a data length of the data block. The read command is for asking whether the corresponding data block is correctly transferred to a transfer destination of the data block. After storing the write commands and the read commands in command language memory region 22, central control equipment 1 instructs line control equipment 5 to start the transfer of the data blocks from buffer memory regions 23.sub.1, 23.sub.2, 23.sub.3 and 23.sub.4 in main memory 2 to a local memory 53 in line control equipment 5.
In line control equipment 5, a transfer controller 51 receives write command WRT.sub.1 from command language memory region 22 through channel control equipment 3 and controls a direct memory access (DMA) controller 52 in accordance with WRT.sub.1 so as to read data block DB.sub.11 from buffer memory region 23.sub.1 and write in local memory 53 through an internal bus 54.
When transfer of data block DB.sub.11 is over, transfer controller 51 successively receives read pattern TRPT.sub.1 from command language memory region 22 and sends a normal acknowledgement called "acknowledgement of normal completed state" ACK.sub.1 to central control equipment 1 if the store of data block DB.sub.11 is correctly performed. Then transfer controller 51 successively receives write command WRT.sub.2 from command language memory region 22 and controls DMA controller 52 so as to read data block DB.sub.12 from buffer memory region 23.sub.2 and store DB.sub.12 in local memory 53 through internal bus 54. When transfer of DB.sub.12 is over, transfer controller 51 successively receives read command TRPT.sub.2 from command language memory region 22 and sends normal acknowledgement ACK.sub.2 to central control equipment 1 if it is verified that DB.sub.12 is correctly stored in local memory 53. Thus, transfer controller 51 successively transfers data blocks DB.sub.13 and DB.sub.14 from buffer memory regions 23.sub.3 and 23.sub.4 to local memory 53 respectively by receiving write commands WRT.sub.3 and WRT.sub.4 from command language memory region 22 respectively and sending normal acknowledgements ACK.sub.13 and ACK.sub.14 to central control equipment 1 every after receiving read patterns TRPT.sub.13 and TRPT.sub.14 respectively. The stored state of data blocks and the process of transferring the data blocks mentioned above are shown in FIGS. 2 and 3 respectively. When the transfer of data blocks DB.sub.11, DB.sub.12, DB.sub.13 and DB.sub.14 is completed, the transferred data blocks are stored in local memory 53 as a stored data D.sub.1 ' having 4 m data length as shown in FIG. 2.
The stored data D.sub.1 ' is restored to packet data D.sub.1 by a processor 55 in line control equipment 5. The headers H.sub.11, H.sub.12, H.sub.13 and H.sub.14 are removed from data blocks DB.sub.11, DB.sub.12, DB.sub.13 and DB.sub.14 respectively and invalid data N.sub.1 is also removed from DB.sub.14 if there is N.sub.1 in DB.sub.14, leaving partial data SD.sub.11, SD.sub.12, SD.sub.13 and SD.sub.14. Then, packet data D.sub.1 having data length n.sub.1 is reproduced by synthesizing the left partial data SD.sub.11, SD.sub.12, SD.sub.13 and SD.sub.14 and forming to a packet. The restored packet data D.sub.1 ' is sent out to a communication network, not depicted in FIG. 1 but connected to data processor 100, by processor 55.